Modern digital technology allows signals to be handled much more easily in digital form than in their analog form. However, it is necessary to convert the received analog signals which are to be handled into their digital form beforehand. Conversely, a digital signal must first be converted into an analog signal before it can be transmitted. For the conversion, “analog/digital converters” or ADCs and the corresponding counterpart DACs for digital/analog converters are used.
So as not to suffer any loss of information when converting an analog signal into a digital signal, the analog signal needs to be sampled, on the basis of the Nyquist criterion, at a frequency which is greater than twice the maximum analog frequency which occurs. At the same time, repetition spectra arise at the multiple of the sampling frequency during sampling. These repetition spectra need to be heavily suppressed as appropriate by a filter.
If the sampling frequency corresponds exactly to the Nyquist criterion, then the sampled spectrum is adjoined by the repetition spectrum directly. Hence, a filter having an almost infinitely high edge gradient is required, which cannot be produced in practice. A sampling rate at a much higher frequency than the Nyquist frequency results in a greater distance between the repetition spectra and allows the use of lower order filters of lesser quality and hence with lower edge gradients.
An analog/digital converter now ascertains the amplitude of the analog signal at a sampling time and converts it into a digital value. In this case, the analog/digital converter divides a maximum amplitude value into subranges of essentially the same magnitude which correspond to the number of bits in the analog/digital converter. By way of example, a maximum occurring voltage amplitude of 1 V is thus divided into 16 stages of 0.125 V each in a 16-bit analog/digital converter.
The analog amplitude signal is compared with the reference values, which assigns an appropriate digital signal. The maximum quantization error is thus half of the difference between two digital reference values, that is to say 62.5 mV in the example. The more precise the division, therefore, the smaller becomes the discrepancy between the result and the analog real value.
One particular embodiment of an analog/digital converter, which is used in digital communication appliances particularly on account of its relatively small demands on the analog suitability of the technology used, is the continuous-time Σ-Δ modulator shown in FIG. 5. This does not convert the analog amplitude signal into a discrete digital value at a sampling time, but rather samples the analog value continuously in the time domain, minimizes the mean-error error over a large number of sampling times, and simultaneously performs filtering (generally high pass filtering) on the quantization errors, which are also called quantization noise.
In this case, the sampling frequency is many times higher than the necessary Nyquist frequency, which means that reference is made to “over sampling” in a general way here. The comparison circuit, the comparator CP in the Σ-Δ modulator shown in FIG. 5, has a signal applied to its input E at one time. This signal is compared with a reference signal at the inverting input of the comparator CP, which means that the comparator outputs a positive or negative binary state at the output.
This signal is firstly processed in a digital decimator and filter DF and is secondly returned to the input of the Σ-Δ modulator via a digital/analog converter DAC. The digital/analog converter DAC converts the digital signal from the comparator into an analog signal using a reference voltage UREF and supplies this analog signal to the input VIN such that the difference between the input signal and the returned signal is formed as a result. This difference signal is integrated and hence averaged in the integrator 3 and is supplied to the input E of the comparison circuit CP again.
The digital decimator DF performs a plurality of tasks. In that part of the Σ-Δ modulator's circuit which is upstream thereof, the quantization noise has not been eliminated, but rather has just been shifted to frequencies outside of the signal band. The first function in the decimator is therefore the filtering of this noise. When this noise has been eliminated, the clock rate can be reduced in the decimator without the risk of infringing the Nyquist theorem. At the same time as the clock rate is reduced, the word length is increased to a number of bits which corresponds at least to the resolution of the converter.
To increase the resolution, the number of integrators 3 can be increased further. This gives the noise transfer function a steeper gradient toward high frequencies, the noise suppression in the signal band being higher on account of the higher gain in the cascaded integrators. Put another way, markedly more effective filtering and hence a lower level of quantization noise in the signal band are achieved.
An example of a “fifth order” Σ-Δ modulator can be seen in FIG. 6. The Σ-Δ modulator contains five integrating circuits, which are denoted by INT1 to INT5. This Σ-Δ modulator is designed using gmC technology and, furthermore, its input VIN has a passive low pass filter which effectively attenuates at least high frequencies and thereby reduces the demands on the active circuit parts downstream.
The drawback of such continuous-time converters, however, is the dependency of the transfer functions and the resolution of time constants, which in ordinary production processes are subject to high levels of scatter of approximately 30%. These are both the usual parameter fluctuations on account of error tolerances in production and temperature responses. Secondly, in usual embodiments with switched current sources in the feedback path, the associated transfer function is dependent on fluctuations in the clock rate itself, known as jitter. In simplified form, jitter corresponds to nonequidistant zero crossings, caused inter alia by thermal noise in the clock generator's components, but also by radiated interference.
Since the integral of the returned signal, generally a current or charge signal, crucially determines the response of the circuit, any clock jitter which is present on the clock signal CLK is incorporated directly into the feedback signal. If, as is generally the case, the amplitude of the feedback signal is also much higher than the amplitude of the input signal, then the sensitivity toward clock jitter is increased even further.
Hence, the document “IEEE Transactions on Circuits and Systems—II: Analogue and Digital Signal Processing, vol. 49, No 11, November 2002: Highspeed Σ-Δ-Modulators with Reduced Timing Jitter Sensitivity” has proposed an arrangement which feeds a cosine square signal as the reference signal into the digital/analog converter DAC. This feedback pulse disappears at the sampling times T, which means that a small amount of clock jitter no longer matters. However, producing two symmetrical cosine signals was found to be extremely difficult and costly in practice.
Another proposal is the arrangement which is described in the document “2003 IEEE International Sold State Circuits Conference/Session 3/Oversampled A/D-Converters/Paper 3.4” and is shown in FIG. 6. In this case, the feedback signal used is the charge which is stored on a switched capacitor. In FIG. 6 of the Σ-Δ modulator designed using gmC technology, these are the capacitors A. A capacitor is discharged in an exponentially decreasing current, which means that at the end of every clock period the current disappears and hence clock jitter no longer matters. A prerequisite for this is that, for the charging and discharging operation, the capacitor has a time constant which is significantly shorter than the corresponding charging and discharging period. In practice, a time constant which is up to eight times shorter, depending on the resolution of the converter 5, than the corresponding charging and discharging period is generally sufficient.
In the arrangement shown in FIG. 6, the forward transfer function is determined by the integrators. The determining variables are the values of the capacitors at the outputs of the gm blocks and also the gradients (gm values) of these blocks. These gradients in turn are determined by transistor parameters and by the reference currents in these blocks. The reference currents are usually derived from a bandgap voltage reference using a reference resistor. Ultimately, the forward transfer function is thus determined by R, C, a reference voltage and transistor parameters. The reverse transfer function, on the other hand, is determined by the charge transferred. This is dependent on the value of the capacitors A and also on the voltage to which these capacitors are charged. In the embodiment shown in FIG. 6, the clock jitter plays no significant part, which was the aim of this circuit. The reverse transfer function is thus ultimately dependent on C and a reference voltage. However, this means that the absolute production variations in the resistors also result in a divergence (mismatch) between the two transfer functions.
The individual components therefore need to be proportioned such that the noise transfer function remains stable even for the most disadvantageous spread, which results in an increase in the noise and in losses in the signal-to-noise ratio, however. The demands for a high level of stability for the converter and simultaneously low noise with little clock jitter sensitivity cannot be met on the basis of this arrangement.